1. Field of the Invention
This invention relates to a circuit and a method for very high-speed multiplexers.
More particularly this invention relates to an arbitrary number of multiple signal multiplexers.
More particularly this invention relates to providing a circuit and a method which converts a parallel data bus into a serial data path.
2. Description of Related Art
The current practice is to use programmable transmission gates to determine which data input (analog or digital signal) is selected to be transmitted to the serial data output. The problem encountered with the prior art is a low and limited data transmission rate. The problems with the transmission gate approach is that parasitic capacitance of multiple gates limits the data speed through the logic gates. The prior art transmission gate design requires careful control of parasitic capacitance, of leakage current and of bus signal collisions.
In addition, the gate level implementation problems of the prior art result in a mismatch between the rise times and fall times of the select signals for the different data paths to be selected. The careful design required to overcome these rise time/fall time mismatches results in degradation of the duty cycle or speed of the serial output of the multiplexer. In order to overcome the rise time/fall time mismatches in the prior art designs, it is required that the system clock have a perfect 50% duty cycle. This is required to avoid glitches between the rise time activation of logic and the fall time activation of logic.
FIG. 1a shows a high level diagram of the prior art multiplexer. The 5-bit data_in bus 120 goes into a transmission gate 110. In addition, a five-bit select bus 130 goes into this transmission gate 110. The serialized, single bit data out 140 comes out of this transmission gate 110.
FIG. 1b shows the gate level implementation of the prior art multiplexer. The parallel data in bus D[4:0] is combined with the data select bus sel [4:0] via NAND gate 160. The five outputs of these NAND gates are combined with a larger, wider NAND gate 150. The output of the wider NAND gate 150 produces the single bit serial output Data Out.
U.S. Pat. No. 5,598,114 (Jamshidi) “High Speed Reduced Area Multiplexer” describes a very high speed multiplexer implemented in a smaller semiconductor area.
U.S. Pat. No. 6,137,340 (Goodell, et al.) “Low Voltage High Speed Multiplexer” shows a low voltage, high speed multiplexer. For a plurality of complementary input pairs, the multiplexer includes a control sub-circuit having a selection switch.
U.S. Pat. No. 6,194,950 (Kibar, et al.) “High-Speed CMOS Multiplexer” shows a high speed CMOS multiplexer constructed only with pass gates and inverters for simple fabrication and higher speed operation.
U.S. Pat. No. 6,239,646 (Navabi, et al.) “High-Speed Multiple-Input Multiplexer Scheme” describes a high speed, multiple-input multiplexer method.